Is Moore’s Law still the law?

Mark Patrick

In 1965, Electronics magazine asked up-and-coming semiconductor research engineer, Gordon Moore, to write about his vision for the future of chip technology.

Moore had noticed the number of transistors on the average IC was doubling every year, from only two in 1959, to “around 60” by 1965 (the rate was later revised to every 18 months). Such rapid growth might have seemed unsustainable, but Moore offered a simple, audacious forecast, since immortalised as ‘Moore’s Law’.

This doubling trend would continue for decades, he said. If he was right, the industry could make long term plans based on the confidence that computer performance, power efficiency and cost-effectiveness would keep improving dramatically, year after year.

Moore now admits that it was “a pretty wild extrapolation”, but the principal dynamics defining the global semiconductor industry that he managed to identify meant that his predictions “turned out to be ridiculously accurate”.

Despite a slight reduction in pace, his law held true for half a century. Meanwhile, the company that Moore co-founded, Intel, profited enormously from a business model based on continual growth and manufacturing innovation, accompanied by the world’s insatiable demand for ever more computing power for products like home computers (broadly predicted, along with self-driving cars and mobile phones, in Moore’s original 1965 article).

By 1971, Intel’s first CPU, the 4004, contained 2,300 transistors (current chips have billions). In the meantime, Moore himself became a wealthy and respected elder statesman of the semiconductor world.

Circuit breaker?

Now, Intel says, Moore’s Law may finally be breaking down, and other major chip makers concur.

Since 2000, although chip transistor counts have continued to climb, maximum clock speed and thermal design power have plateaued. Chipmakers have begun to fall behind schedule when it comes to the introduction of ever smaller process technologies, which have long been the primary engine delivering higher transistor counts, as well as performance and operational efficiency improvements.

Smaller transistors can switch faster and they require less power, so the industry is deeply concerned by the deceleration (as manufacturers struggle to shrink chip features from 14nm through 10nm towards 5nm).

For end users, the effect of this slow down takes two main forms. First the bottleneck in traditional single-threaded computing processes. If a critical part of a program cannot be run on a faster CPU and cannot be parallelised, then there may be no way to make it finish faster. This impinges on performance.

Second, thermal control technologies are being pushed to the limit as larger die sizes and more densely-packed components make it ever harder to move heat away from sensitive areas.

Manufacturing solutions

On the manufacturing side, researchers are following multiple angles of attack as they try to keep semiconductor development moving forward.

First among those is an old standby for the industry: new materials and manufacturing techniques. Intriguing compounds that may partly replace the traditional silicon in chips include graphene, silicon-germanium and gallium alloys.

However, while these offer new opportunities by which to enhance performance, they still raise technical challenges, such as differing thermal properties that can lead to some of the materials splintering away from the silicon substrate, thus reducing production yields.

Other manufacturers are moving up into three dimensions, at both a micro and macro level.

Transistor performance is improved by raising the transistor source above the substrate, onto the same layer as the gate, increasing the surface area of the connection between them. This finfet transistor, first introduced by Intel at the 22nm stage, improves switching speed by one third and simultaneously halves power consumption.

Samsung is working on an evolution of this process, in which the gate actually surrounds the source. The company predicts this could be the key that eventually unlocks 5nm IC production.

At the macro level, chips are stacked and layered in three dimensions to pack more functional capacity into a smaller space and reduce communication delays.

While linking the chips together remains difficult, this technique is already common in memory chips, but it is more of a problem for hot-running CPUs and GPUs. Some researchers are looking at advanced liquid cooling that pumps coolant through micro-channels in the core of the chip.

End users

At the other end of the manufacturing chain, closer to the end user, designers and software developers are learning to do more with the hardware they have, because they can no longer assume problems will be smoothed out when a new generation of faster chips arrives.

Software developers are rethinking processes and programming paradigms to parallelise them if possible.

This approach meshes neatly with developments in artificial intelligence and deep learning, building smarter systems rather than relying simply on brute force.

Systems integrators and end users can find ways to distribute computing power and the internet of things (IoT) is a prime target for this. If devices can pre-process data to avoid overloading central servers, potential computing logjams can be avoided.

Meanwhile, Moore points out that his law has been declared dead before (even by himself), and still holds out hope that new technologies could continue to bring increases in raw computing performance.

Reminiscing in 2014 he said: “There have been a variety of potential barriers… that looking forward a couple of generations looked formidable. But as we approached them, enough engineering had been put in place to eliminate the barrier or get around it.”

About The Author

Mark Patrick is supplier marketing manager at Mouser Electronics. He joined Mouser Electronics in 2014 from RS Components and before that worked for Texas Instruments.